1. Field of the Invention
The present invention relates to communication, and more particularly, a method and apparatus for modulating and spreading communication signals.
2. Description of Related Art
Digital communication relies on numerous different, albeit related, forms of digital modulation such as phase shift keying (PSK), bi-phase shift keying (BPSK), quadrature phase shift keying (QPSK or 4-PSK), and quadrature amplitude modulation (QAM).
BPSK will be described with reference to FIG. 1. As shown, the magnitude of a reference carrier is constant, and to transmit either a 0 or a 1, the phase thereof is “keyed” or switched between 0° and 180°. A receiver then decides whether a 0 or a 1 was transmitted based on the phase of the received carrier, and generates the original data stream. With this simple scheme, one bit of information is transmitted with each state or symbol, so that the carrier phase is keyed at the data rate. FIG. 1 also illustrates the constellation for BPSK. As shown, the BPSK constellation diagram includes two points in the I-Q plane where I stands for in-phase (i.e., phase reference) and Q stands for quadrature (i.e., 90° out-of-phase). The two points in the BPSK constellation diagram represent the position of the signal at the “timing instance”. The timing instance is when the receiver interprets the signal. The signal can only be at one position at a time, but the constellation can be thought of as having persistence so that all of the proper states appear. Constellation diagrams such as in FIG. 1 typically do not show the transition between states and it should be noted that this transition does take a finite time. But for clarity, the transitions are not shown otherwise traces connecting the two states would clutter the diagram. Furthermore, instead of being located on the I-axis, the constellation points could, for example, lie on the Q-axis.
FIG. 2 illustrates the constellation diagram for QPSK. As shown, four different states exist in the QPSK diagram at, for example, phase values of 45°, 135°, 225°, and 315°. As further shown, each state corresponds to a symbol representing two bits. Because the data is taken two bits at a time to form a symbol, the symbol rate is half the bit rate. As a result, QPSK requires half the band width of BPSK for the same bit rate.
FIG. 3 illustrates the constellation for 16-QAM (quadrature amplitude modulation). In addition to modulating the phase, the amplitude of the signal is also modulated to create four distinct constellation points within each quadrant of the I-Q plane. As shown, in 16-QAM, one symbol represents four bits of data.
FIG. 4 illustrates a prior art architecture for spreading and modulating data for transmission. As shown, a serial-to-parallel converter 10 converts the serial data to parallel. A modulation mapper 15 then maps the parallel data to respective symbols in the I-Q plane. For example, the modulation mapper 15 may map one type of channel according to QPSK and a different type of channel according to 16 QAM. For the example of QPSK, the serial-to parallel converter 1-10 converts serial data into respective pairs of parallel data. The modulation mapper 15, may map the binary value of “0” to the real value of +1, and the binary value of “1” to the real value of −1.
However, the modulation mapper 15 also receives I and Q DTX control signals DTXI and DTXQ. As is known, DTX stands for discontinued transmission (i.e., no transmission). Accordingly, if the I DTX control signal DTXI is asserted (e.g., DTXI is 0), the modulation mapper 15 outputs the real value of 0 as the I signal. Likewise, if the Q DTX control signal DTXQ is asserted (DTXQ is 0), the modulation mapper 15 outputs the real value of 0 as the Q signal. If the I DTX control signal DTXI and/or the Q DTX control signal DTXQ are not asserted (e.g., DTXI and/or DTIXQ is 1), then the modulation mapper 15 outputs the I and/or Q signals based on the received parallel data. As is known, instead of having separate DTX control signals for the I signal and the Q signal, a single DTX control signal may be used.
Next, the I and Q signals output from the modulation mapper 15 undergo spreading by a spreading unit 80. The spreading unit 80 includes a channelization operation and a scrambling operation. In the channelization operation, the I and Q data are multiplied with a channelization code Cch,SF,m by respective multipliers 20 and 25. Here, ch indicates the code C is a channelization code, SF is the spreading factor (described below) and m is the code number (also described below). The channelization operation transforms each data symbol into a number of chips, thus increasing the bandwidth of the signal. The number of chips per data symbol is called the spreading factor (SF).
Channelization codes may be Orthogonal Variable Spreading Factor (OVSF) codes that preserve orthogonality between different signals. The OVSF codes may be defined using the code tree of FIG. 5. As shown, the channelization codes are uniquely described as Cch,SF,m, where SF is the spreading factor of the code and m is the code number 0<=m<=SF−1. Namely, each code tree defines channelization codes of length SF, corresponding to a spreading factor of SF as shown in FIG. 5, and each channelization code of spreading factor SF may have SF code patterns uniquely identified by the code number m.
After channelization, the Q signal is shifted 90 degrees from the I signal by the multiplier 30, and a summer 35 sums the I and Q signals. As a result, the summation signal includes a total of eight chips for the pair of parallel input bits—four chips on the I signal portion and four chips on the Q signal portion. A multiplier 40 scrambles the summation signal output by the summer 35 by multiplying the summation signal with a scrambling code S. Namely, the sequence of complex valued chips are scrambled (complex chip-wise multiplication) by a complex-valued scrambling code S.
The scrambled summation signal is then modulated by a modulation unit 90. The modulation unit 90 includes a splitter 45 that splits the scrambled summation signal into real and imaginary parts. Respective pulse shapers 50 and 55 pulse shape the real and imaginary signals, respectively. Modulation is completed by mixing the real signal with a cos (wt) signal at multiplier 60 and the imaginary signal with a −sin (wt) signal at multiplier 65. A summer 70 sums the modulated signals to produce a signal for transmission.
Conventionally, the channelization, scrambling and modulation operations in the architecture of FIG. 4 are implemented in an application specific integrated circuit (ASIC). However, most third generation wireless communication standards create significant challenges in designing and developing architectures for baseband processing as described above with respect to FIG. 4. Add to this the fact that most of these standards are evolutionary, and it will be appreciated that creating such architectures is like hitting a moving target.